As a method for improving system performance of LSI, technology for integrating a logic circuit and a DRAM on the same semiconductor chip has been conventionally examined. On the other hand, in a single logic circuit configured mainly based on an MOSFET, to achieve high performance, an SOI-MOSFET using a thin-film SOI substrate in place of a conventional bulk silicon substrate has been examined and already put into production for an intended purpose of some of high-performance logic devices, and its superiority has been proved. In such a situation, taking further improvement of performance into account, development of LSI having a DRAM mixedly mounted on a high-performance logic chip, which has a logic circuit mounted on an SOI substrate, can be considered.
However, it is considered that mounting both the logic circuit and the DRAM has the following problem.
In an SOI-MOSFET, since the potential in a body region where a channel is formed floats due to presence of a BOX film, a fluctuation in characteristics, e.g., a leak current or a threshold value involved by a circuit operation may possibly occur owing to a floating-body effect. Therefore, like a cell transistor of a DRAM or a sense amplifier circuit, it is considered that mixed mounting is unsuitable for application to a circuit that has rigorous demands for, e.g., a leak current level or unevenness of a threshold value.
To solve this problem of the floating-body effect, an extraction device region from a body portion and a contact must be provided with respect to an MOSFET pattern and the body potential must be controlled, but there is a problem that a cell area or an area of a sense amplifier unit is thereby greatly increased, and high integration, which is the greatest characteristics of the DRAM, is deteriorated.
As countermeasures for this problem, various kinds of methods for forming a circuit unit, which is incompatible with the floating-body effect, in a non-SOI region by providing the non-SOI region on an SOI substrate (which is also referred to as partial SOI) have been also suggested.
For example, there is a method for partially removing an SOI layer and a buried insulator layer (a BOX layer) of an SOI substrate by etching, performing selective epitaxial growth of silicon in the etching region, and effecting polishing and flattening to form a non-SOI region (e.g., see Patent Literature 1). Further, there is also a method for forming a non-SOI region in which a bulk region is surrounded by an insulative spacer and a conductive spacer, overcoming a floating-body effect, and electrically separating an SOI region from the non-SOI region (see, e.g., Patent Literature 2).
However, in regard to any method, there is no detailed description concerning a configuration of the SOI substrate and a configuration of the BOX layer in the SOI region, and a method for more easily manufacturing a partial SOI substrate has been demanded.